The present invention relates to a binary data storage device. More particularly, the present invention relates to a technology that may be applied conveniently to a semiconductor storage device, such as a RAM (Random Access Memory) and a ROM (Read Only Memory), which is connected to a data processor such as a microprocessor or a microcomputer and to or from which data is written or read one byte (8 bits), one word (16 bits), and an integral multiple of 8 bits at a time.
As the operation frequency or the data processing power (number of data bits) of a microprocessor or a microcomputer that accesses a semiconductor storage device increases, there is a need for a higher-speed semiconductor storage device.
To satisfy this need, various technologies have been proposed to increase the speed of a semiconductor storage device. Examples of those technologies are found in JP-A-6-332793 or in IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS, PP. 190-201, 1999. However, the conventional technique to increase the speed of a semiconductor storage device has placed emphasis on device miniaturization or on the increase in speed of a memory cell circuit from which data is read. Those technologies do not take into consideration the relation with a data processor, such as a microprocessor or a microcomputer, to which the semiconductor storage device is connected.
Normally, the configuration of a semiconductor storage device is such that the read/write operation can be performed at a time for the number of data bits basically used by a data processor, such as a microprocessor or a microcomputer, connected to the semiconductor storage device. For example, a semiconductor storage device connected to a data processor whose basic data length is 32 bits is configured such that data is read or written efficiently 32 bits at a time. Similarly, a semiconductor storage device connected to a data processor whose basic data length is 64 bits is configured such that data is read or written efficiently 64 bits at a time.
Because an address is allocated to each byte (8 bits) of data in a common data processor, a semiconductor device connected to the data processor is designed to read and write data on an address number basis. In addition, for the read data length, the semiconductor storage device is designed so that data which is xc2xdn times (n is an integer equal to or larger than 1) the basic data length and which is 8 bits or longer must be able to be read or written. That is, for the basic data length of 32 bits, 16 bits (32xc3x97xc2xd1 bits), or 2 bytes, and 8 bits (32xc3x97xc2xd2 bits), or 1 byte, must be able to be read or written. This will be described more in detail with reference to the drawings.
FIG. 3 schematically shows the physical array of data stored in a conventional semiconductor storage device connected to a data processor whose basic data length is 32 bits (4 bytes) and the logical operation executed when 32 bits of data is read from the storage device. The numeral 300 indicates data stored in the semiconductor storage device, and the numeral 301 indicates data read from the semiconductor storage device. In this case, 32 bits of data is read directly. That is, the semiconductor storage device is laid out and wired so that the relative distance between the nth bit of the data in the semiconductor storage device and the nth bit of the register into which the data is read becomes shortest.
FIG. 4 schematically shows the physical array of data stored in a conventional semiconductor storage device connected to a data processor whose basic data length is 32 bits (4 bytes) and the logical operation executed when 16 bits (2 bytes) of data are read from the storage device. The numeral 400 indicates data stored in the semiconductor storage device, and the numerals 401 and 402 indicate data read from the semiconductor storage device.
FIG. 4(a) shows how the low-order 16 bits (byte 1 and byte 0) of the data 400 are read, and FIG. 4(b) shows how the high-order 16 bits (bytes 3, byte 2) of the data 400 are read. It should be noted that, in FIG. 4(b), the bit shift operation is required for 16 bits, from the high-order 16 bits to the low-order 16 bits. In a conventional semiconductor storage device, the memory cell array is laid out in the data bit sequence. Therefore, to execute the operation shown in FIG. 4(b), the data must be physically shifted 16 bits. That is, in FIG. 4(a), the relative distance between the nth bit (0xe2x89xa6nxe2x89xa615) of the semiconductor storage device and the nth bit (0xe2x89xa6nxe2x89xa615) of the register into which data is read is shortest. On the other hand, in FIG. 4(b), the relative wiring length becomes longer because the nxe2x80x2th bit (16xe2x89xa6nxe2x80x2xe2x89xa631)of the semiconductor storage device is stored in the nth bit (0xe2x89xa6nxe2x89xa615)of the register into which data is read. This lengthens the wiring length, increases the wiring load, reduces the read speed, and increases the power consumption.
FIG. 5 schematically shows the physical array of data stored in a conventional semiconductor storage device connected to a data processor whose basic data length is 32 bits (4 bytes) and the logical operation executed when 8 bits (1 byte) of data are read from the storage device. The numeral 500 indicates data stored in the semiconductor storage device, and the numerals 501, 502, 503, and 504 indicate data read from the semiconductor storage device.
FIG. 5(a) shows how the 8 bits corresponding to byte 0 of the data 500 are read, FIG. 5(b) shows how the 8 bits corresponding to byte 1 of the data 500 are read, FIG. 5(c) shows how the 8 bits corresponding to byte 2 of the data 500 are read, and FIG. 5(d) shows how the 8 bits corresponding to byte 3 of the data 500 are read. It should be noted that the bit shift operation is required for 8 bits from byte 1 to byte 0 in FIG. 5(b), that the bit shift operation is required for 16 bits from byte 2 to byte 0 in FIG. 5(c), and that the bit shift operation is required for 24 bits from byte 3 to byte 0 in FIG. 5(b), respectively.
In a conventional semiconductor storage device, a memory cell array is laid out in data bit sequence. Therefore, when executing operation as shown in FIG. 5(b), FIG. 5(c), or FIG. 5(d), the 8-bit, 16-bit, or 24-bit physical shift operation must be executed, respectively. That is, as in FIG. 4(b), the relative wiring length becomes longer. This layout lengthens the wiring from each memory cell to the selector, increases the wiring load, reduces the read speed, and increases the power consumption. In addition, because 24 bit-shift signal lines sometimes run in parallel in some part of the above example as shown in FIG. 16(a), there are some problems; for example, the wiring area is increased, and the signal lines are so dense that they cause crosstalk between signal lines. On the other hand, there is another method in which data is always read into a register at memory access time, 32 bits at a time, and then only the necessary number of bits of the data are extracted by shifting the bits. However, this method requires a time for bit shift processing and thus reduces the read speed.
It is an object of the present invention to provide a storage device that solves the above problems, that reads or writes even data shorter than the basic data length, for example, reads 8 bits of data (that is, byte) speedily, and that requires less power.
It is another object of the present invention to provide a storage device that reduces an area occupied by the wiring and that minimizes the generation of crosstalk.
The above and other objects and the new features of the present invention will be made more apparent by the description in the specification and the accompanying drawings.
The overview of the typical contents of the present invention disclosed in this application will be described below.
That is, a storage device comprises a memory cell array comprising a plurality of memory cells; word lines used to select memory cells from the plurality of memory cells in response to an address signal; and bit lines used to read information stored in the selected memory cells, wherein the storage device is connected to an address bus and a data bus, and wherein a bit array of data stored in the memory array is different from a bit array in the data bus.
Information pieces transmitted via adjacent bit signal lines on the data bus are stored in the memory cells a predetermined number of bits apart.
In addition, more specifically, when a basic read unit is n bits, information pieces, whose logical bit positions are 0*8+k, 1*8+k, 2*8+k, 3*8+k, . . . , m*8+k (where k and m are natural numbers, 0xe2x89xa6kxe2x89xa67 and 0xe2x89xa6mxe2x89xa6n/8xe2x88x921), are stored in the memory cells close to one another in the memory cell array.
The means described above makes the wiring length for the bit shift operation at read time extremely short and therefore reads data speedily in units of bytes. At the same time, the means significantly reduces the amount of devices and wiring used to build a circuit for executing the bit shift operation, making a low-power storage device available. In addition, because the wiring length for the bit shift operation at data read time is relatively short, the means reduces both the area occupied by wiring and the number of signal lines running in parallel in the wiring area for the bit shift operation. Therefore, the means gives a storage device with a minimized wiring area and reduced crosstalk.